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ATmega128
System Clock
and Clock
Options
Clock Systems
and their
Distribution
Figure 18 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in “Power Manage-
ment and Sleep Modes” on page 44 . The clock systems are detailed below.
Figure 18. Clock Distribution
Asynchronous
Timer/Counter
General I/O
modules
ADC
CPU Core
RAM
Flash and
EEPROM
clk ADC
clk I/O
clk ASY
AVR Clock
Control Unit
clk CPU
clk FLASH
Reset Logic
Source clock
Clock
Multiplexer
Watchdog Timer
Watchdog clock
Watchdog
Oscillator
Timer/Counter
External RC
Crystal
Low-Frequency
Calibrated RC
Oscillator
Oscillator
External clock
Oscillator
Crystal Oscillator
Oscillator
CPU Clock – clk CPU
I/O Clock – clk I/O
Flash Clock – clk FLASH
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that address recognition in the T W I module is carried out asynchro-
nously when clk I/O is halted, enabling T W I address reception in all sleep modes.
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
35
2467X–AVR–06/11
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